In general, in the conventional art, the outer leads of a semiconductor device and the wiring portions of a circuit board are bonded together by soldering. A conventional semiconductor device having conventional gull-wing and straight outer leads and a manufacturing method of such a semiconductor device are described, for example, in Susumu Kohyama et al. (eds.), ASIC Packaging Technology Handbook, Science Forum Inc., pp. 206-209.
In order to strengthen the bond between the outer leads of a semiconductor device and the circuit board on which it is mounted, and to thereby ensure reliable connection, it is necessary to provide a large solder fillet. The xe2x80x9csolder filletxe2x80x9d is a solder portion rising from the surface of the wiring portion toward the outer lead. Since the size of the solder fillet is dependent on the electrode area of the board, it is required that that electrode area be as great as possible. At the same time, however, there is a demand for higher integration density and the use of a larger number of pins. To prevent the adjacent electrodes from short-circuiting due to the solder provided, the intervals at which the electrodes are arranged must be greater than a certain distance, and the electrodes are not allowed to have sufficient dimensions in the width direction of the outer leads. In general, therefore, the electrodes are designed to have substantially the same widths as the outer leads and to have sufficient dimensions in the longitudinal direction of the outer leads, since the electrodes of this structure enable the required solder fillets to be provided.
For the reasons given above, a solder fillet is not formed in the regions on the side of the solder portion of the outer leads since the electrodes formed on the board are not allowed to have sufficient space in those regions. Therefore, in the case of a QFP (Quad Flat Package) type, a SOP (Small Outline Package) type or another type of semiconductor device having gull wing-shaped outer leads, each outer lead has only two solder portions: one is the distal end and the other is the proximal end. In general, the solder fillet at the distal end of a lead is referred to as a front fillet, while that at the proximal end thereof is referred to as a back fillet.
The conventional art will be described with reference to FIGS. 1A-1D, FIGS. 2A-2E and FIGS. 3-6. FIGS. 1A-1D show a first example of a manufacturing process of a conventional QFP or SOP type semiconductor device. As shown in FIG. 1A, a resin-molded semiconductor package 101 has an outer lead 102 extending in the horizontal direction, and the distal end of that outer lead is connected to the outer frame (not shown) of a lead frame.
As shown in FIG. 1B, a solder plating 103 is provided on the surface of the outer lead 102 by electroplating, for example.
Next, the distal end portion of the outer lead 102 is cut off to disconnect the semiconductor package 101 from the lead frame, as shown in FIG. 1C. Further, the outer lead is bent by means of a punch, as shown in FIG. 1D.
FIGS. 2A-2E show a second example of a manufacturing process of a conventional QFP or SOP type semiconductor device. Like the example shown in FIG. 1A, a semiconductor package 101 has an outer lead 102.
As shown in FIG. 2B, a solder plating 103 is provided on the surface of the outer lead 102 by electroplating, for example. Next, the distal end portion of the outer lead 102 is cut off to disconnect the semiconductor package 101 from the lead frame, as shown in FIG. 1C. At the time, the outer lead 102 extending from the package 101 is made to include an auxiliary portion; in other words, the length of the outer lead 102 that remains after cutting is slightly greater than the final length. The outer lead 102 is cut by the shearing stress that is applied thereto when a cut punch is moved downward. Thereafter, the outer lead is bent in the manner shown in FIG. 2D. Finally, the distal end portion of the outer lead 102 is cut off a gain, as shown in FIG. 2E.
Each of the outer leads 102 of the conventional QFP or SOP type semiconductor device worked as above has such a distal end as is shown in FIG. 3. As shown, the distal end has a cut face formed in the lead cutting process. To improve the solder characteristics, the outer lead 102 is normally provided with an outer sheath, and a typical method used for this purpose is electroplating, in which current flows through the frame. It should be noted that the outer lead 102 cannot be provided with a solder plating layer unless it is electrically connected to the lead frame. Therefore, the solder plating process must be executed before the distal end portion of each outer lead is cut off. As can be seen from this, the cut face at the distal end of each outer lead 102 of the conventional QFP or SOP type semiconductor device is not provided with a plating layer, as shown in FIG. 3.
When the outer leads are soldered to the board, the cut face at the distal end of an outer lead is not covered with a soldering material. As shown in FIG. 4, the front fillet 104 is, at the highest, half the thickness of the outer lead.
In the examples given above, the distal ends of the outer leads are cut in a direction that prevents the resultant burrs from protruding toward the surface of the board. Unless the distal ends of the outer leads are cut in such a direction, the front fillet 104 described above cannot be formed.
If the solder fillet is less than half the thickness of an outer lead, it is not possible to provide sufficient bonding strength. In the conventional QFP or SOP type, therefore, most of the bonding strength with reference to the board is dependent only on the back fillet 104xe2x80x2. However, in the case of a semiconductor device which must undergo complex stress, as at the time when a temperature cycle test is executed, the bonding strength based only on the back fillet 104xe2x80x2 is not considered reliable.
Visual inspection, by which to check whether sufficient solder fillets have been formed and whether soldering has been completed in a desirable manner, is normally executed by observing the devices on the board from above through a microscope. However, since the back fillets 104xe2x80x2 are blocked from view due to the outer leads 102 when observation is made in this direction, only the shapes of the front fillets 104 are observed in the visual inspection, and judgment is made based on them. As shown in FIG. 4, however, the front fillets 104 are small in the case of the conventional QFP or SOP type, so that the visual inspection is not easy and requires a long time.
As shown in FIG. 5, an SON (Small Outline Non Leaded Package) is one type of packages having straight outer leads. Due to the structural features, no back fillets 104xe2x80x2 are not formed in the case of the SON, as can be seen from FIG. 6. In addition, the fillets 104 at the distal ends of the leads are not sufficient to provide reliable bonding, for the same reasons as described above in regard to the QFP and SOP type. In the case of the SON type semiconductor device, wherein no back fillets are formed, the insufficient front fillets 104 become a cause of unreliable bonding strength. The conventional SON structure is not applicable to a semiconductor device that is required of high reliability.
In regard to the SON structure, it should be noted that the amount of solder used for forming the fillets is small in comparison with the case of QFP or SOP type. In particular, if the front fillets 104 are small in size, all solder paste coated on the electrodes on the board may not be used, resulting in short-circuiting between the adjacent electrodes.
The present invention has been made in due consideration of the above problems, and the object of the invention is to provide a semiconductor device which enables formation of sufficient front fillets, reliable bonding strength with reference to electrodes on a board, and easy visual inspection.
According to the present invention, this object is achieved by providing a semiconductor device, comprising: means for providing outer leads which extend outward from within a package that seals a semiconductor chip and which are connected to the semiconductor chip inside the package; means for forming depressions in the distal end portions of the outer leads; and means for coating the depressions with one material selected from the group including Snxe2x80x94Pb, Snxe2x80x94Ag, Snxe2x80x94Bi, Snxe2x80x94Zn, Snxe2x80x94Cu, Pd, Au and Ag.
With this structure, the semiconductor device can be reliably soldered to a circuit board, both front and back solder fillets can be formed on the wiring electrodes and outer leads in an optimal manner, and the electric and mechanical connections are therefore very reliable.
According to the present invention, there is also provided a semiconductor device-manufacturing method comprising the steps of: providing outer leads which extend outward from within a package that seals a semiconductor chip and which are connected to the semiconductor chip inside the package; forming depressions in those portions of the outer leads which are to become distal end portions after the outer leads are cut; executing one of electrolytic plating, electroless plating, hot dipping and deposition with respect to the outer leads; and cutting off distal ends of the outer leads such that the depressions are partly left in cut end faces of the outer leads.
Owing to the above steps, the semiconductor device can be reliably soldered to a circuit board, both front and back solder fillets can be formed on the wiring electrodes and outer leads in an optimal manner, and the electric and mechanical connections are therefore very reliable.
According to the present invention, there is further provided a semiconductor device-manufacturing method comprising the steps of: providing outer leads which extend outward from within a package that seals a semiconductor chip and which are connected to the semiconductor chip inside the package; executing one of electrolytic plating, electroless plating, hot dipping and deposition with respect to the outer leads; forming depressions in those portions of the outer leads which are to become distal end portions of the outer leads after the outer leads are cut; and cutting the distal end portions of the outer leads such that the depressions are partly left in cut end faces of the outer leads.
Owing to the above steps, the solder characteristics of the outer leads are improved, and solder fillets can be formed on the electrodes on the circuit board in an optimal manner, thus enhancing the reliability. In addition, the cut positions can be determined with a high degree of freedom.
According to the present invention, there is further provided a semiconductor device-manufacturing method comprising the steps of: providing outer leads which extend outward from within a package that seals a semiconductor chip and which are connected to the semiconductor chip inside the package; executing one of electrolytic plating, electroless plating, hot dipping and deposition with respect to the outer leads; cutting the outer leads; working the outer leads to have a predetermined shape; forming depressions in the outer leads; and cutting the outer leads at positions corresponding to the depressions.
Owing to the above steps, the solder characteristics are improved, and solder fillets can be formed on the outer leads at both the front and back positions, thus enhancing the reliability.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.